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NB4N840M 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination
Description
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The NB4N840M is a high-bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for applications such as SDH/SONET, DWDM, Gigabit Ethernet and high speed switching. Fully differential design techniques are used to minimize jitter accumulation, crosstalk, and signal skew, which make this device ideal for loop-through and protection channel switching applications. Internally terminated differential CML inputs accept AC-coupled LVPECL (Positive ECL) or direct coupled CML signals. By providing internal 50 W input and output termination resistor, the need for external components is eliminated and interface reflections are minimized. Differential 16 mA CML outputs provide matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC. Single-ended LVCMOS/LVTTL SEL inputs control the routing of the signals through the crosspoint switch which makes this device configurable as 1:2 fan-out, repeater or 2 x 2 crosspoint switch. The device is housed in a low profile 5 x 5 mm 32-pin QFN package.
Features
1
32
QFN32 MN SUFFIX CASE 488AM A WL YY WW G
DA0 DA0 CML
NB4N 840M ALYWG
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
0 CML 1 QA0 ENA0 SELA0 0 QA1 CML QA1 ENA1 SELA1 QA0
DA1 DA1
CML
1
DB0 DB0
CML
0 1
QB0 CML QB0 ENB0 SELB0
* * * * * * * * * * * * *
Plug-in compatible to the MAX3840 and SY55859L Maximum Input Clock Frequency 2.7 GHz Maximum Input Data Frequency 3.2 Gb/s 225 ps Typical Propagation Delay 80 ps Typical Rise and Fall Times 7 ps Channel to Channel Skew 430 mW Power Consumption < 0.5 ps RMS Jitter 7 ps Peak-to-Peak Data Dependent Jitter Power Saving Feature with Disabled Outputs Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V CML Output Level (400 mV Peak-to-Peak Output), Differential Output These are Pb-Free Devices
0 DB1 DB1 CML 1 CML
QB1 QB1 ENB1 SELB1
Figure 1. Functional Block Diagram ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
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August, 2006 - Rev. 2
Publication Order Number: NB4N840M/D
NB4N840M
Table 1. TRUTH TABLE
SELA0/SELB0 L L H H X SELA1/SELB1 L H L H X ENA0/ENA1 H H H H L ENB0/ENB1 H H H H L QA0/QB0 DA0/DB0 DA0/DB0 DA1/DB1 DA1/DB1 Disable/Power Down QA1/QB1 DA0/DB0 DA1/DB1 DA0/DB0 DA1/DB1 Disable/Power Down Function 1:2 Fanout Quad Repeater Crosspoint Switch 1:2 Fanout No output (@ VCC)
SELA0
32 ENB1 DB1 DB1 ENB0 SELB0 DB0 DB0 SELB1 1 2 3 4
31
30
29
28
27
26
25 24 23 22 21 GND VCC QA0 QA0 VCC QA1 QA1 VCC
NB4N840M 5 6 7 8 9 GND 10 VCC 11 QB0 12 QB0 13 VCC 14 QB1 15 QB1 16 VCC 20 19 18 17
Figure 2. Pin Configuration (Top View)
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SELA1
ENA1
ENA0
DA1
DA1
DA0
DA0
NB4N840M
Table 2. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9,24 10, 13, 16, 17, 20, 23 11 12 14 15 18 19 21 22 25 26 27 28 29 30 31 32 - Name ENB1 DB1 DB1 ENB0 SELB0 DB0 DB0 SELB1 GND VCC QB0 QB0 QB1 QB1 QA1 QA1 QA0 QA0 SELA1 DA0 DA0 SELA0 ENA0 DA1 DA1 ENA1 EP I/O LVTTL CML Input CML Input LVTTL LVTTL CML Input CML Input LVTTL - - CML Output CML Output CML Output CML Output CML Output CML Output CML Output CML Output LVTTL CML Input CML Input LVTTL LVTTL CML Input CML Input LVTTL GND Description Channel B1 Output Enable. LVTTL low input powers down B1 output stage. Channel B1 Positive Signal Input Channel B1 Negative Signal Input Channel B0 Output Enable. LVTTL low input powers down B0 output stage. Channel B0 Output Select. See Table 1. Channel B0 Positive Signal Input Channel B0 Negative Signal Input Channel B1 Output Select. See Table 1. Supply Ground. All GND pins must be externally connected to power supply to guarantee proper operation. Positive Supply. All VCC pins must be externally connected to power supply to guarantee proper operation. Channel B0 Negative Output. Channel B0 Positive Output. Channel B1 Negative Output. Channel B1 Positive Output. Channel A1 Negative Output. Channel A1 Positive Output. Channel A0 Negative Output. Channel A0 Positive Output. Channel A1 Output Select, LVTTL Input. See Table 1. Channel A0 Positive Signal Input. Channel A0 Negative Signal Input. Channel A0 Output Select, LVTTL Input. See Table 1. Channel A0 Output Enable. LVTTL low input powers down A0 output stage. Channel A1 Positive Signal Input. Channel A1 Negative Signal Input. Channel A1 Output Enable. LVTTL low input powers down A1 output stage. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit. The exposed pad must be soldered to the circuit board GND for proper electrical and thermal operation.
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NB4N840M
Table 3. ATTRIBUTES
Characteristics ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Human Body Model Machine Model QFN-32 Oxygen Index: 28 to 34 Value > 2000 V > 110 V Level 1 UL 94 V-0 @ 0.125 in 380
Table 4. MAXIMUM RATINGS
Symbol VCC VI VINPP IIN IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Differential Input Voltage |D - D| Static Surge Continuous Surge QFN-32 Condition 1 GND = 0 V GND = 0 V GND = VI = VCC Condition 2 Rating 3.8 3.8 3.8 45 80 25 80 -40 to +85 -65 to +150 0 lfpm 500 lfpm 2S2P (Note 3) <3 sec @ 260 C QFN-32 QFN-32 QFN-32 31 27 12 260 Unit V V V mA mA mA mA C C C/W C/W C/W C
Input Current Through Internal 50 W Resistor Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 2) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4N840M
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 3.0 V to 3.6 V, TA = -40C to +85C
Symbol ICC Voutdiff VCMR (Note 6) VID Characteristic Power Supply Current (All outputs enabled) CML Differential Output Swing (Note 4, Figures 5 and 12) CML Output Common Mode Voltage (Loaded 50 W to VCC) CML Single-Ended Input Voltage Range Differential Input Voltage (VIHD - VILD) VCC - 0.8 300 640 Min Typ 130 800 VCC - 200 VCC + 0.4 1600 Max 170 1000 Unit mA mV mV mV mV
LVTTL CONTROL INPUT PINS VIH VIL IIH IIL RTIN RTOUT Input HIGH Voltage (LVTTL Inputs) Input LOW Voltage (LVTTL Inputs) Input HIGH Current (LVTTL Inputs) Input LOW Current (LVTTL Inputs) CML Single-Ended Input Resistance Differential Output Resistance -10 -10 42.5 85 50 100 2000 800 10 10 57.5 115 mV mV mA mA W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. CML outputs require 50 W receiver termination resistors to VCC for proper operation (Figure 10). 5. Input and output parameters vary 1:1 with VCC. 6. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V (Note 7, Figure 9)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) (See Figure 3) Maximum Operating Data Rate Propagation Delay to Output Differential D/D to Q/Q Duty Cycle Skew (Note 8) Within-Device Skew (Figure 4) Device-to-Device Skew (Note 12) RMS Random Clock Jitter (Note 10) Peak-to-Peak Data Dependent Jitter (Note 11) fin v 3.2 GHz fin = 2.5 Gb/s fin = 3.2 Gb/s 140 225 5 5 20 0.15 7 7 340 25 25 85 0.5 20 20 0.5 150 Q, Q 80 800 135 150 80 140 225 5 5 20 0.15 7 7 340 25 25 85 0.5 20 20 0.5 800 135 150 80 140 225 5 5 20 0.15 7 7 340 25 25 85 0.5 20 20 0.5 800 135 ps fin 2 GHz fin 3 GHz fin 3.5 GHz Min 280 235 170 3.2 Typ 365 310 220 Max Min 280 235 170 3.2 25C Typ 365 310 220 Max Min 280 235 170 3.2 85C Typ 365 310 220 Max Unit mV
fDATA tPLH, tPHL tSKEW
Gb/s ps
tJITTER
ps
Crosstalk-Induced RMS Jitter (Note 13) VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 9) Output Rise/Fall Times @ 0.5 GHz (20% - 80%)
ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% - 80%). 8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.5 GHz. 9. VINPP (MAX) cannot exceed 800 mV. Input voltage swing is a single-ended measurement operating in differential mode. 10. Additive RMS jitter using 50% duty cycle clock input signal. 11. Additive peak-to-peak data dependent jitter using input data pattern with PRBS 223-1 and K28.5, VINPP = 400 mV. 12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Data taken on the same device under identical condition.
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NB4N840M
OUTPUT VOLTAGE AMPLITUDE (mV) 450 400 350 300 TIME (ps) 250 200 150 100 50 0 0.05 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 INPUT CLOCK FREQUENCY (GHz) 20 18 16 14 12 10 8 6 4 2 0 -40 25 TEMPERATURE (C) 85 Channel B Channel A
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fIN) at Ambient Temperature (Typ)
900 800 700 CURRENT (mA) VOLTAGE (mV) 600 500 400 300 200 120 100 0 -40 25 TEMPERATURE (C) 85 160 150 140 130 170
Figure 4. Within-Device Skew vs. Temperature at VCC = 3.3 V
110 -40
25 TEMPERATURE (C)
85
Figure 5. CML Differential Voltage vs. Temperature
Figure 6. Supply Current vs. Temperature (All 4 Outputs Enabled)
VOLTAGE (50 mV/div)
VOLTAGE (50 mV/div)
DDJ = 4 ps
DDJ = 3 ps
TIME (80.4 ps/div)
TIME (62.5 ps/div)
Figure 7. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (Input Signal DDJ = 12 ps)
Figure 8. Typical Output Waveform at 3.2 Gb/s with K28.5 (Input Signal DDJ = 14 ps)
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NB4N840M
Dx VINPP = VIH(DX) - VIL(DX) Dx Qx VOUTPP = VOH(QX) - VOL(QX) Qx tPHL tPLH
Figure 9. AC Reference Measurement
VCC
50 W Q Driver Device Q Zo = 50 W Zo = 50 W
50 W D Receiver Device D
Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8057/D)
VCC
VCC
50 W
50 W
50 W
50 W QX
DX
QX
DX
16 mA
GND Input
GND
GND Output
Figure 11. CML Input and Output Structure
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NB4N840M
640 mV MIN QX 320 mV MIN QX (QX - QX)
QX
1000 mV MAX 500 mV MAX
QX (QX - QX)
Figure 12. CML Output Levels
ORDERING INFORMATION
Device NB4N840MMNG NB4N840MMNR4G Package QFN32 (Pb-Free) QFN32 (Pb-Free) Shipping 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4N840M
PACKAGE DIMENSIONS
D
A B
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
32 X b 0.10 C A B
0.05 C BOTTOM VIEW
32 X
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW D2
9 8 16 17 1 32 25
PIN ONE LOCATION
E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
(A3) A A1 C
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
EXPOSED PAD
K
32 X
5.30 3.20
E2
24
32 X
0.63
e
3.20
5.30
0.28
28 X
0.50 PITCH *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB4N840M/D

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